TLE94106EL Datasheet, PDF (41/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
Serial Peripheral Interface (SPI)
Table 10 Failure reported in the Global Status Register and Global Error Flag
Type of Error
Failure reported in the Global
Status Register
Global Error Flag
Thermal Warning
TPW = 1
1
No Error and no Power ON Reset SPI_ERR = 0
0
LE = 0
VS_UV = 0
VS_OV = 0
NPOR = 1
TSD = 0
TPW = 0
Note:
The default value (after Power ON Reset) of NPOR is 0, therefore the default value of GEF is 1.
7.1.3 SPI protocol error detection
The SPI incorporates an error flag in the Global Status Register (SPI_ERR, Bit7) to supervise and preserve the
data integrity. If an SPI protocol error is detected during a given frame, the SPI_ERR bit is set in the next SPI
communication.
The SPI_ERR bit is set in the following error conditions:
• the number of SCLK clock pulses received when CSN is Low is not 0, or is not a multiple of 8 and at least 16
• the microcontroller sends an SPI command to an unused address. In particular, SDI stuck to High is
reported in the SPI_ERR bit
• the LSB of an address byte is not set to 1. In particular, SDI stuck to Low is reported in the SPI_ERR bit
• the Last Address Bit Token (LABT, bit 1 of the address byte, see Chapter 7.2) in independent slave
configuration is not set to 1
• the LABT bit of the last address byte in daisy chain configuration is not set to 1 (see Chapter 7.3)
• a clock polarity error is detected (see Figure 17 Case 2 and Case 3): the incoming clock signal was High
during CSN rising or falling edges.
For a correct SPI communication:
• SCLK must be Low for a minimum t_BEF before CSN falling edge and t_lead after CSN falling edge
• SCLK must be Low for a minimum t_lag before CSN rising edge and t_BEH after CSN rising edge
Data Sheet
41
1.0
2016-09-08