TLE94106EL Datasheet, PDF (49/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
Serial Peripheral Interface (SPI)
SPI Frame 1
Overcurrent failure detected on HS of HB 1 SPI frame: Read SYS _DIAG2 (OC error of HB 1-4)
LSB
Address Byte
Data Byte
MSB
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SDI
1
LABT A2
=1 =0
A3
=0
A4
=1
A5
=1
A6
=0
OP
=0
X
X
X
X
X
X
X
X
Overcurrent failure detected on HS of HB 1 during the
transfer of the address byte
Target status register : OC error of HB 1-4
LSB
Global Status Register
Response Data Byte : SYS_DIAG2 _MSB
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SDO
0
TPW
TSD NPOR VS_OV VS_UV
LE
=0
SPI_
ERR
D0
=0
D1
=1
D2
=0
D3
=0
D4
=0
D5
=0
D6
=0
D7
=0
Load Error bit (Overcurrent or Open Load )
does not report the new Overcurrent failure
HB1_HS_OC reports the new
Overcurrent failure on the HS of HB 1
Inconsistency between Global Status Register
and target Status Register
Time
SPI frame 2 (new)
New SPI frame : e.g. Read SYS _DIAG2 (OC error of HB 1-4)
LSB
Address Byte
Data Byte
MSB
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
1
LABT A2
=1 =0
A3
=0
A4
=1
A5
=1
A6
=0
OP
=0
X
X
X
X
X
X
X
X
Target status register : OC error of HB 1-4
LSB
Global Status Register
Response Data Byte : SYS_DIAG2 _MSB
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
TPW
TSD NPOR VS_OV VS_UV
LE
=1
SPI_
ERR
D0
=0
D1
=1
D2
=0
D3
=0
D4
=0
D5
=0
D6
=0
D7
=0
Consistent information : Both Load Error bit and HB 1_HS_OC report
the Overcurrent failure detected during the previous SPI frame
Figure 24 Example of inconsistency between Global Error Flag and Status Register when a status bit
is changed during the transfer of an address byte
Data Sheet
49
1.0
2016-09-08