TLE94106EL Datasheet, PDF (23/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
General Description
5
General Description
5.1
Power Supply
The TLE94106EL has two power supply inputs, V_S and V_DD. The half bridge outputs are supplied by V_S, which is
connected to the 12V automotive supply rail. V_DD is used to supply the I/O buffers and internal voltage
regulator of the device.
V_S and V_DD supplies are separated so that information stored in the logic block remains intact in the event of
voltage drop outs or disturbances on V_S. The system can therefore continue to operate once V_S has recovered,
without having to resend commands to the device.
A rising edge on V_DD crossing V_{DD POR} triggers an internal Power-On Reset (POR) to initialize the IC at power-on.
All data stored internally is deleted, and the outputs are switched off (high impedance).
An electrolytic and 100nF ceramic capacitors are recommended to be placed as close as possible to the V_S
supply pin of the device for improved EMC performance in the high and low frequency band. The electrolytic
capacitor must be dimensioned to prevent the VS voltage from exceeding the absolute maximum rating. In
addition, decoupling capacitors are recommended on the V_DD supply pin.
5.2
Operation modes
5.2.1 Normal mode
The TLE94106EL enters normal mode by setting the EN input High. In normal mode, the charge pump is active
and all output transistors can be configured via SPI.
5.2.2 Sleep mode
The TLE94106EL enters sleep mode by setting the EN input Low. The EN input has an internal pull-down
resistor.
In sleep mode, all output transistors are turned off and the SPI register banks are reset. The current
consumption is reduced to I_SQ + I_{DD_Q}.
5.3
Reset Behaviour
The following reset triggers have been implemented in the TLE94106EL:
V_DD Undervoltage Reset:
The SPI Interface shall not function if V_DD is below the undervoltage threshold, V_{DD POffR}. The digital block will
be deactivated, the logic contents cleared and the output stages are switched off . The digital block is
initialized once V_DD voltage levels is above the undervoltage threshold, V_{DD POR}. Then the NPOR bit is reset
(NPOR = 0 in SYS_DIAG1 and Global Status Register).
Reset on EN pin:
If the EN pin is pulled Low, the logic content is reset and the device enters sleep mode.
The reset event is reported by the NPOR bit (NPOR = 0) once the TLE94106EL is in normal mode (EN = High; VDD
> V_{DD POR}).
Data Sheet
23
1.0
2016-09-08