TLE94106EL Datasheet, PDF (45/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
Serial Peripheral Interface (SPI)
7.3
Daisy chain operation
The TLE94106EL supports daisy chain operation with devices with the same SPI protocol.This section
describes the daisy chain hardware configuration with three devices from the TLE941xy family (See
Figure 20).
The master output (noted MO) is connected to a slave SDI and the first slave SDO is connected to the next slave
SDI to form a chain. The SDO of the final slave in the chain will be connected to the master input (MI) to close
the loop of the SPI communication frame. In daisy chain configuration, a single chip select, CSN, and clock
signal, SCLK, connected in parallel to each slave device, are used by the microcontroller to control or access
the SPI devices.
In this configuration, the Master Output must send the address bytes and data bytes in the following order:
• All address bytes must be sent first:
– Address Byte 1 (for TLE941xy_1) is sent first, followed by Address Byte 2 (for TLE941xy_2) etc,...
– The LABT bit of the last address byte must be 1, while the LABT bit of all the other address bytes must
be 0
• The data bytes are sent all together once all address bytes have been transmitted: Data Byte 1 (for
TLE941xy_1) is sent first, followed by Data Byte 2 (for TLE941xy_2) etc,...
Note:
The signal on the SDI pin of the first IC in daisy chain (and in non-daisy chain mode), must be Low at
the beginning of the SPI frame (between CSN falling edge and the first SCLK rising edge). This is
because each Global Error Flag in daisy chain operation is implemented in OR logic.
The Master Input (MI), which is connected to the SDO of the last device in the daisy chain receives:
• A logic OR combination of all Global Error Flags (GEF), at the beginning of the SPI frame, between CSN
falling edge and the first SCLK rising edge
• The logic OR combination of the GEFs is followed by the Global Status Registers in reverse order. In other
words MI receives first the Global Status Register of the last device of the daisy chain
• Once all Global Status Registers are received, MI receives the response bytes corresponding to the
respective address and data bytes in reverse order. For example, if the daisy chain consists of three devices
with SDO or TLE941xy_3 connected to MI, the master receives first the Response Byte 3 of TLE941xy_3
(corresponding to Address Byte 3 and Data Byte 3) followed by the Response Byte 2 of TLE941xy_2 and
finally the Response Byte 1 of TLE941xy_1.
An example of an SPI frame with three devices from the TLE941xy family is shown in Figure 21.
Data Sheet
45
1.0
2016-09-08