TLE94106EL Datasheet, PDF (40/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
Serial Peripheral Interface (SPI)
CSN
SCLK
SDI
SDO
0
0
High Impedance _{Global Error Flag}
time
time
time
High Impedance
time
Figure 16 SDO behaviour with 0-clock cycle
7.1.2 Global Status Register
The SDO shifts out during the first eight SCLK cycles the Global Status Register. This register provides an
overview of the device status. All failures conditions are reported in this byte:
• SPI protocol error (SPI_ERR)
• Load Error (LE bit): logical OR between Open Load (OL) and Overcurrent (OC) failures
• VS Undervoltage (VS_UV bit)
• VS Overvoltage (VS_OV bit)
• Negated Power ON Reset (NPOR bit)
• Temperature Shutdown (TSD bit)
• Temperature Pre-Warning (TPW bit)
See Chapter 7.7.1 for details.
Note:
The Global Error Flag is a logic OR combination of every bit of the Global Status Register with the
exception of NPOR: GEF = (SPI_ERR) OR (LE) OR (VS_UV) OR (VS_OV) OR (NOT(NPOR)) OR (TSD) OR
(TPW).
The following table shows how failures are reported in the Global Status Register and by the Global Error Flag.
Table 10 Failure reported in the Global Status Register and Global Error Flag
Type of Error
Failure reported in the Global
Status Register
Global Error Flag
SPI protocol error
SPI_ERR = 1
1
Open load or Overcurrent
LE = 1
1
VS Undervoltage
VS_UV = 1
1
VS Overvoltage
VS_OV = 1
1
Power ON Reset
NPOR = 0
1
Thermal Shutdown
TSD = 1
1
Data Sheet
40
1.0
2016-09-08