TLE94106EL Datasheet, PDF (48/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
Serial Peripheral Interface (SPI)
No information is lost, even if a status register is changed during a SPI frame, in particular during a Read and
Clear command. For example:
• the microcontroller sends a Read and Clear command to a status register
• the TLE94106EL detects during the transfer the data byte(s) a new fault condition, which is normally
reported in the target status register
The incoming Clear command will be ignored, so that the microcontroller can read the new failure in the
subsequent SPI frames.
Data inconsistency between the Global Status Register (see Chapter 7.7) and the data byte (status register)
within the same SPI frame is possible if:
• an open load or overcurrent error is detected during the transfer of the data byte
• the target status register corresponds to the new detected failure
In this case the new failure:
• is not reported in the Global Status Register of the current SPI frame but in the next one
• is reported in the data byte of the current SPI frame
Refer to Figure 23.
Data Sheet
48
1.0
2016-09-08