IC-MN_16 Datasheet, PDF (58/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
BiSS Profile
MODE_ST
NBISS
ELC
GRAY_SCD
DL_ST
DL_MT
M2S
R_MT
R_ST
SBL_x
Notes
24-24
0x00-0x0B (Nonius)
0
0
0
0x10 (24)
0x0D (24)
0x03
0x18 (24)
UBL_M+UBL_S+UBL_N
̸= 0x00
UBL_M+UBL_S+UBL_N ≤ 24
Table 109: Setup for BiSS profile 24-24
BiSS Profile
MODE_ST
NBISS
ELC
GRAY_SCD
DL_ST
DL_MT
M2S
R_MT
R_ST
SBL_x
Notes
24-24++
0x00-0x0B (Nonius)
0
0
0
0x11(25)
0x0D (24)
0x03
0x18 (24)
0x19 (25)
̸= 0x00
UBL_M=13, UBL_S=6, UBL_N=6
Table 110: Setup for BiSS profile 24-24++
Remarks to iC-MN with EDS:
Rev F2, Page 58/62
1. CFG_E2P ̸= b000 (i.e. bank switch function has
been activated.)
2. EDSBANK must be set 0x03 (no other values are
possible)
Addressing via BiSS: Bank: 2, Adr: 0x01
or direct to EEPROM: Adr: 0x081
3. Set profile ID.
Addressing via BiSS: Bank: 2, Adr: 0x02-0x03
or direct to EEPROM: Adr: 0x082-0x083
APPLICATION NOTES: PLC Operation
PLC Operation
There are PLCs with a remote sense supply which re-
quire longer for the voltage regulation to settle. At the
same time the PLC inputs can have high-impedance
resistances versus an internal, negative supply voltage
which define the input potential for open inputs.
In this instance iC-MN’s reverse polarity protection fea-
ture can be activated as the outputs are tristate during
the start phase and the resistances in the PLC deter-
mine the pin potential. During the start phase neither
the supply VDD nor the output pins, which are also mon-
itored, must fall to below ground potential (pin GND);
otherwise the device is not configured and the outputs
remain permanently set to tristate.
In order to ensure that iC-MN starts with the PLCs
mentioned above pull-up resistors can be used in the
encoder. Values of 100 kΩ are usually sufficient; it
is, however, recommended that PLC specifications be
specifically referred to here.