IC-MN_16 Datasheet, PDF (5/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
PACKAGING INFORMATION
Rev F2, Page 5/62
PIN CONFIGURATION QFN48-7x7
PIN FUNCTIONS
No. Name Function
1 NSINS Signal Input Sine - (Segment)
2 PSINS Signal Input Sine + (Segment)
3 PCINS Signal Input Cosine + (Segment)
4 NCINS Signal Input Cosine - (Segment)
5 NSINM Signal Input Sine - (Master)
6 PSINM Signal Input Sine + (Master)
7 PCINM Signal Input Cosine+ (Master)
8 NCINM Signal Input Cosine - (Master)
9 NSINN Signal Input Sine - (Nonius)
10 PSINN Signal Input Sine + (Nonius)
11 PCINN Signal Input Cosine + (Nonius)
12 NCINN Signal Input Cosine - (Nonius)
13 n.c.
14 n.c.
15 n.c.
16 n.c.
17 DIR Sense of Rotation Preselection Input,
Calibration Signal IPB
18 PRES Preset Input
19 SCL EEPROM Interface, clock line
20 SDA EEPROM Interface, data line
PIN FUNCTIONS
No. Name Function
21 MAO I/O Interface, clock output
22 SLI
I/O Interface, data input
23 NMA* I/O Interface, clock input -
24 MA*
I/O Interface, clock input +
25 NSLO* I/O Interface, data output -
26 SLO* I/O Interface, data output +
27 MTSLI Multiturn Interface, data input
28 T3
External Trigger Input,
Test Signal Input
29 MTMA Multiturn Interface, clock output
30 T2
Test Signal Input
31 GND* Ground
32 VDD* +4.5 to 5.5 V Supply Voltage
33 NERR* Error Message Output,
System Error Message Input
34 n.c.
35 n.c.
36 n.c.
37 NSOUT* Analog Output Sine - (Master)
38 PSOUT* Analog Output Sine + (Master)
39 NCOUT* Analog Output Cosine - (Master)
40 PCOUT* Analog Output Cosine + (Master)
41 T0
Test Signal Output
42 T1
Test Signal Output
43 ACOM* Signal Level Controller Outp. (Master)
44 VACO* +4.5 to 5.5 V Signal Level Controller
Supply
45 ACON* Signal Level Controller Output
46 ACOS* Signal Level Controller Output,
VREFin Ref. Voltage Input/Output
47 GNDA Sub-System Ground Output
48 VDDA Sub-System Positive Supply Output
*:
n.c. :
Pin is immune against faulty output
or supply connection.
Pin is not connected.
Connecting pin VACO to VDD is mandatory. Wiring unused input pins can be recommended, especially for pins
SLI, DIR, PRES and T2 (to GNDA). For calibrating the internal bias current source a pull-down resistor of 5 kΩ
±1 % connected from pin DIR to GNDA is useful (see Figure 10).
To improve heat dissipation the thermal pad of the QFN package (bottom side) should be joined to an extended
copper area which must have GNDA potential.