IC-MN_16 Datasheet, PDF (35/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
TRACK OFFSET CALIBRATION
Rev F2, Page 35/62
Depending on the track resolution the offset values of
the nonius and segment tracks (POV = Phase-Offset-
Value) must be justified to the left in the SPO_N and
SPO_S registers. These offsets are added to the con-
version result of each track prior to synchronization and
are instrumental in calibrating the track.
SPO_N
SPO_S
0x0000
...
0x1FFF
Addr. 0x3B; bit 1:0
Addr. 0x3A; bit 7:0
Addr. 0x39; bit 7:5
Addr. 0x39; bit 4:0
Addr. 0x38; bit 7:0
Track Offset
datalength defined by UBL_x+SBL_x
SPO_x MSB
register: ^POV_x
LSB
POV_x
0
0
0
S: ADR 0x39, bit 4
N: ADR 0x3B, bit 1
Figure 14: SPO_x (x=S,N)
S: ADR 0x38, bit 0
N: ADR 0x39, bit 5
Table 49: Track offsets for nonius and segment
Note:
For nonius synchronization (see MODE_ST) it is im-
portant that the used tracks within the 2^UBL_S+UBL_N
master track periods have a shared zero crossing
once. With SPO_S or SPO_N the segment and non-
ius tracks can be shifted to the master track accord-
ingly.