IC-MN_16 Datasheet, PDF(23/62 Page) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

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IC-MN_16 Datasheet, PDF (23/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

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iC-MN 25-BIT NONIUS ENCODER

WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

Rev F2, Page 23/62

SIGNAL CONDITIONING for MASTER-, SEGMENT- and NONIUS-Channel (x= M,S,N)

DCPOS

Code

Addr. 0x0A; bit 6

Polarity Isensor

VREFin()

Negative

2.5 V

Positive

1.5 V

Table 12: Input current polarity

RIN

Code

Addr. 0x0A; bit 2:1

Resistance

1.6 kâ¦

2.3 kâ¦

3.2 kâ¦

4.6 kâ¦

Table 13: Input resistance with I mode

Figure 7: Schematic of Input Stage

The input stages for sine and cosine are instrumen-

tation amplifiers and can process current and voltage

signals; selection is made for all three tracks using UIN.

Signal conditioning should be performed in the order

given in the following.

Voltage Signals

If the voltage signals are too large the input signal can

be quartered by an internal divider. The voltage divider

is referenced to the VREFin reference source which is

set by DCPOS. In order to use the input voltage range

of the input amplifier to its full capacity DCPOS should

be set to 1 in voltage divider mode.

TUIN

Code

Addr. 0x0A; bit 3

Function

Not active

Voltage divider active

UIN

Code

Addr. 0x0A; bit 0

Function

I Mode: current inputs

V Mode: voltage inputs

Table 11: Signal mode

Table 14: Input voltage divider

Additionally, using CVREF the user can select whether

VREFin is the reference potential generated internally

or a voltage provided externally.

CVREF

Code

Note

Addr. 0x0B; bit 4:3

Function

Generated internally

Reserved

Internal VREFin() output to pin ACOS*

External ref. voltage supplied to pin ACOS

*) No load permitted, buffer required.

Figure 8: Direction of current flow

Table 15: VREF Source Selection

Current Signals

For current signals internal reference VREFin is

adapted to the input current polarity using DCPOS. The

input resistance is set using RIN (1:0). When select-

ing the input resistance the average potentials SVDC

and CVDC should be between 125 mV and 250 mV to

obtain a reasonable offset calibration range.

All other settings are to be carried out for each individual

track separately. A small x in the register name stands

for (M)aster, (S)egment and (N)onius respectively.

Gain Adjustment

The gain is set in three stages. The gain range is

first determined for sine and cosine using register

GR_x (2:0). Register GFC_x (4:0) can then be used

▷