IC-MN_16 Datasheet, PDF (32/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev F2, Page 32/62
UBL_N/
UBL_S
2
3
4
5
6
SBL_N/
SBL_S
2
3
4
2
3
4
2
3
4
2
3
4
2
3
4
Permissible Max. Phase Deviation
[given in degree per signal period of 360°]
+/- 22.5°
+/- 33.75°
+/- 39.38°
+/- 11.25°
+/- 16.88°
+/- 19.69°
+/- 5.63°
+/- 8.44°
+/- 9.84°
+/- 2.81°
+/- 4.22°
+/- 4.92°
+/- 1.41°
+/- 2.11°
+/- 2.46°
Table 45: Tolerable phase deviation for the master ver-
sus the nonius or segment track (with refer-
ence to 360°, electrical)
The synchronization principle is summarized in Figure
11, where φ represents the digitized angle of the rele-
vant track.
Digital Frequency Monitoring
iC-MN features an integrated frequency monitoring cir-
cuit for the master track. A signal frequency warning
threshold can be configured by FRQ_TH.
FRQ_TH
Code
00
01
10
11
Addr. 0x43; bit 7:6
Warning Threshold
7.625 kHz
31.25 kHz
62.5 kHz
125 kHz
Table 46: Signal frequency monitoring
FRQ_TH is used by the frequency-dependent period
verification feature available for nonius modes (see
MODE_ST = 0x01, 0x03, 0x06 and 0x09).
The following applies to all modes with nonius synchro-
nization: if the frequency of the master track is too high
at power on, FRQ_STUP and FRQ_WDR remain set
until the period verification was successful below the
frequency warning threshold. In nonius modes without
an enabled period verification it must be observed that
FRQ_STUP remains permanently set and can only be
reset by SOFT_RES when the warning threshold is
undershot.
Figure 11: Principle of nonius mode synchronization