IC-MN_16 Datasheet, PDF (55/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
iC-MN internal
linear address-
space divided into n
banks of size 64
byte
ADR
0x00
address-space visible via BiSS
(CFG_E2P > 000)
bank n-1
(e.g. CFG_E2P > 101; n=32)
bank 3
...
bank 2
ADR
0x00
bank 1
bank 0
0x3F
0x40
Rev F2, Page 55/62
0x7F
0x80
0xBF
0xC0
0xFF
0x3F
0x40
0x7F
BANKSEL
EDSBANK
profile ID
serial number
SLAVE-registers
STATUS
BiSS-ID
selects
Figure 30: Principle of bank-wise memory addressing
Register access can be restricted via PROT_E2P (see
Table 100). PROT_E2P = 10 selects safety level 2, a
shipping mode with limited access. Shipping 2 can be
set back to level 1 (shipping 1), for which purpose the
content of address 0x43 must be written anew.
PROT_E2P(1:0) Addr. 0x43; bit 1:0
Code
Mode
Access Limitation
(see Figure 31 and 32)
00
Configuration Mode, free RP0
access
01
Configuration Mode,
RP1
limited access
10
Shipping Mode 1,
RP2
reset to RP1 is possible
11
Shipping Mode 2,
RP2
reset is not possible
Table 100: Register Access Control
Sections CONF, EDS and USER are protected at differ-
ent levels in shipping mode for read and write access.
PROT_E2P(1:0) Addr. 0x43; bit 1:0
Range
RPL*
CONF
EDS
RP0
r/w
r/w
RP1
STATUS n/a r/w
r/w for others
RP2
n/a
r only
Note
* Register Protection Level
USER
r/w
r/w
r/w
Table 101: Register Read/Write Protection Levels
(n/a: iC-MN refuses access to those register
addresses.)
Figure 31 shows the static memory area and Figure
32 the area which can be altered by BANKSEL. The
BiSS register access limitations which are generated by
parameter PROT_E2P are marked ”R/W” for read/write
access and ”R” for read only. The original site of data
returned by access to the BiSS register is designated
by ”RAM” for iC-MN’s internal RAM, by ”E2P” for the
EEPROM and by ”INT” for those of iC-MN’s internal
registers which cannot be preloaded on startup.