IC-MN_16 Datasheet, PDF (15/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev F2, Page 15/62
OPERATING REQUIREMENTS: I/O Interface
Operating conditions: VDD = 5 V ±10 %, Ta = -40...110 °C,
IBP calibrated for fosc = 8 MHz, reference point GNDA (GND for digital I/O pins), unless otherwise stated
Item Symbol Parameter
No.
Conditions
Min.
Unit
Max.
SSI Protocol
I001
I002
I003
I004
T_MAS
t_MASh
t_MASl
t_cycle
Permissible Clock Period
Clock Signal Hi Level Duration
Clock Signal Lo Level Duration
Permissible Cycle Time:
Example for 19-bit ST data from
3-track nonius calculation
t_out selected in accordance to Table 50
MODE_ST = 0x05...0x07,
UBL_M = 13 bit, UBL_N + SBL_N = 7 bit,
UBL_S + SBL_S = 7 bit
250
2x t_out
ns
25
t_out
ns
25
t_out
ns
11.25
µs
BiSS C Protocol (NBISS = 0x0)
I005
I006
I007
I008
T_MAS
t_MASh
t_MASl
t_busy
Permissible Clock Period
Clock Signal Hi Level Duration
Clock Signal Lo Level Duration
Minimum Data Output Delay
t_out selected in accordance to Table 58
MODE_ST = 0x05...0x0B, 0x0D...0x0F,
MA lo→hi until SLO lo→hi
100
ns
25
t_out
ns
25
ns
2x T_MAS
µs
I009 t_busy
I010 t_busy
I011 t_busy
I012 t_cycle
Maximum Data Output Delay:
Example for 19-bit ST data from
3-track nonius calculation
Maximum Data Output Delay:
Example for 19-bit ST data from
3-track nonius calculation
Maximum Data Output Delay:
Example for 39-bit ST data from
3-track interpolation without
synchronization
Permissible Cycle Time:
Example for 19-bit ST data from
3-track nonius calculation
MODE_ST = 0x00...0x02, fclk(MA) = 10 MHz,
UBL_x and SBL_x see I004
MODE_ST = 0x03...0x04, fclk(MA) = 10 MHz,
UBL_x and SBL_x see I004
MODE_ST = 0x0C, fclk(MA) = 10 MHz,
UBL_M 13 bit, UBL_N 13 bit, UBL_S 13 bit
5.3
µs
10
µs
14
µs
MODE_ST = 0x05...0x07,
UBL_x and SBL_x see I004
11.25
µs
Figure 1: I/O Interface timing with SSI protocol
Figure 2: I/O Interface timing with BiSS C protocol