IC-MN_16 Datasheet, PDF (31/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev F2, Page 31/62
1. With a data readout: immediate transmission of
the data from the last readout cycle including the
relevant NON_CTR
2. With a data readout: start of a new conversion
and providing of data for the next data readout
cycle. NON_CTR is output directly at the NERR
pin.
Principle PPR And Bit Length Dependencies
With a nonius system with three tracks UBL_M must
be set so that it is at least as large as the maximum
value of MAX(UBL_S+SBL_S, UBL_N+SBL_N). If only
two tracks are used, UBL_S and SBL_S must be set
to zero. UBL_M must then at least match the maximal
value of MAX(UBL_N+SBL_N).
MODE_ST Codes 0x08, 0x09, 0xA
The processing time is low and the time of sampling
not precisely known. The conversion procedure is as
follows:
The necessary number of signal periods per revolu-
tion for the individual tracks is then determined by the
selected used bit lengths:
1. Regardless of the data readout: permanent back-
ground conversion
2. With a data readout: transmission of current data.
Each NON_CTR is output directly at the NERR
pin. In data transmission a NON_CTR error is
only signaled when the error occurs during the
relevant nonius calculation.
MODE_ST Code 0x0B
This mode can be used in systems in which sampling
must be synchronized to a frequency determined exter-
nally and independent of the data readout cycles. The
sampling will be started with a rising edge at pin T3.
The conversion procedure is as follows:
Track
Master
Segment
Nonius
Required signal periods
2^UBL_S+UBL_N
2^UBL_S+UBL_N − 2^UBL_N
2^UBL_S+UBL_N − 1
The following tables show the possible settings and
required number of signal periods. The total physical
angle resolution in nonius mode is obtained from the
sum of UBL_M+UBL_S+UBL_N. At the same time the
bit lengths set for synchronization determine a limit up
to which a nonius calculation is possible. This limit
is given in Table 45 as the maximum tolerable phase
deviation which may occur between the segment and
master track or nonius and master track (with reference
to the electrical 360° period of the master signal).
1. A conversion with nonius synchronization is trig-
gered via a rising edge at pin T3. NON_CTR is
output directly at the NERR pin.
2. With a data readout the most recent conversion
data triggered by pin T3 is transmitted including
the relevant NON_CTR.
Bits/Track
Signal periods/Turn
Physical
resolution ^a)
UBL_S UBL_N Master Segm. Nonius min ^b) max
2
2
16
12
15
2+2+4 2+2+13
3
2
32
28
31
2+3+5 2+3+13
3
3
64
56
63
3+3+5 3+3+13
4
3
128 120 127 3+4+6 3+4+13
4
4
256 240 255 4+4+6 4+4+13
5
4
512 496 511 4+5+7 4+5+13
5
5
1024 992 1023 5+5+7 5+5+13
6
5
2048 2016 2047 5+6+8 5+6+13
6
6
4096 4032 4095 6+6+8 6+6+13
a_{) For configuration of the output data length, see Table 51}
b_{) For the minimum data length SBL_x = 0x02 is assumed}
Table 43: Settings for 3-track nonius mode
Bits/Track Signal periods/Turn Physical resolution ^a)
UBL_N Master Nonius min ^b)
max
4
16
15
4+6
4+13
5
32
31
5+7
5+13
6
64
63
6+8
6+13
a_{) For configuration of the output data length, see Table 51}
b_{) For the minimum data length SBL_x = 0x02 is assumed}
Table 44: Settings for 2-track nonius mode