IC-MN_16 Datasheet, PDF (12/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev F2, Page 12/62
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,
IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated
Item Symbol Parameter
No.
Conditions
I/O Interface: RS422 Line Driver Outputs SLO, NSLO
E01 Vs()hi
Saturation Voltage hi
Vs() = VDD − V();
DSC(1:0) = 11, I() = -1.2 mA
DSC(1:0) = 10, I() = -4 mA
DSC(1:0) = 01, I() = -20 mA
DSC(1:0) = 00, I() = -50 mA
E02 Vs()lo
Saturation Voltage lo
DSC(1:0) = 11, I() = 1.2 mA
DSC(1:0) = 10, I() = 4 mA
DSC(1:0) = 01, I() = 20 mA
DSC(1:0) = 00, I() = 50 mA
E03 Isc()hi
Short-circuit Current hi
V() = 0 V;
DSC(1:0) = 11
DSC(1:0) = 10
DSC(1:0) = 01
DSC(1:0) = 00
E04 Isc()lo
Short-circuit Current lo
V() = VDD
DSC(1:0) = 11
DSC(1:0) = 10
DSC(1:0) = 01
DSC(1:0) = 00
E05 Ilk()tri
Tristate Leakage Current
DTRI(1:0) = 11
E06 tr()
Rise Time hi
RL = 100 Ω to GND, DSC(1:0) = 00;
DSR(1:0) = 00
DSR(1:0) = 01
DSR(1:0) = 10
DSR(1:0) = 11
E07 tf()
Fall Time lo
RL = 100 Ω to VDD, DSC(1:0) = 00;
DSR(1:0) = 00
DSR(1:0) = 01
DSR(1:0) = 10
DSR(1:0) = 11
E08 Ilk()
Residual Current with Reverse
Polarity
I/O Interface: RS422 Line Receiver MA, NMA
F01 Vin()
Permissible Input Voltage
F02 Rin()
Input Resistance
MA vs. GND, NMA vs. GND
F03 Vhys() Differential Input Hysteresis
Vhys() = ( V(MA) - V(NMA) ) / 2
F04 Vt()hi
Input Threshold Voltage hi at MA pin NMA open
F05 Vt()lo
Input Threshold Voltage lo at MA pin NMA open
F06 fclk()
Permissible Clock Frequency:
SSI protocol
MODE_ST = 0x05 to 0x0B, 0x0D to 0x0F
F07 fclk()
Permissible Clock Frequency: NBISS = 0
BiSS protocol
F08 tp(MA-SLO) Propagation Delay:
MA edge vs. SLO output
RL(SLO/NSLO) = 120 Ω
F09 tbusy_s
Processing Time Singlecycle
Data (delay of start bit)
Nonius modes:
MODE_ST = 0x00 to 0x02
MODE_ST = 0x03 to 0x04, 2 track
MODE_ST = 0x03 to 0x04, 3 track
MODE_ST = 0x05 to 0x0B
MT modes:
MODE_ST = 0x0C, 3 track
MODE_ST = 0x0D to 0x0F
F10 tbusy_r
Processing Time Register Access with read access to EEPROM
(delay of start bit)
F11 tidle
Interface Blocking Time
powering up without EEPROM
Unit
Min. Typ. Max.
-3
-10
-45
-120
1.2
4
20
50
-10
10
22
60
250
5
22
60
250
-100
200 mV
200 mV
400 mV
900 mV
200 mV
200 mV
400 mV
900 mV
-1.2 mA
-4
mA
-20 mA
-50 mA
3
mA
10
mA
45
mA
120 mA
10
µA
30
ns
40
ns
140
ns
350
ns
15
ns
40
ns
140
ns
350
ns
100 µA
-7
12
V
15
20
25
kΩ
50
200 mV
2
V
800
mV
4
MHz
10 MHz
10
50
ns
tcnv *1
µs
tcnv *2
µs
tcnv *3
µs
0
µs
tcnv *3
µs
0
µs
2
ms
2
ms