IC-MN_16 Datasheet, PDF (30/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
S/D CONVERSION with NONIUS CALCULATION
Rev F2, Page 30/62
For the nonius modes iC-MN has a flash counter which
counts the zero crossings of the master track. When
the system is started this flash counter is preloaded
with the absolute period information which has been
most recently calculated using the nonius and segment
tracks (or only the nonius track).
culation. If the limit is again undershot, future
conversions are again verified.
3. Period verification versus nonius calculation is
always enabled and executed with each conver-
sion.
The output data word always is the flash counter value
synchronized with the master track. Furthermore, it is
possible to output synchronized singleturn and multi-
turn position data which can be set using the parameter
MODE_MT (see page 47).
MODE_ST
Addr. 0x3D; bit 7:4
Operation modes with nonius calculation (Nonius Modes)
Code
Description
Data outp. following S/D conversion of master track
0x00
Period verification disabled
0x01
Frequency-dependent period verification
0x02
Period verification enabled
Data output following S/D conversion of all tracks
0x03
Frequency-dependent period verification
0x04
Period verification enabled
Zero-delay data output: result of previously triggered
S/D conversion
0x05
Period verification disabled
0x06
Frequency-dependent period verification
0x07
Period verification enabled
Zero-delay data output: last result of background
S/D conversion (asynchronous)
0x08
Period verification disabled
0x09
Frequency-dependent period verification
0x0A
Period verification enabled
Zero-delay data output: last result of S/D conversion
triggered by pin T3
0x0B
Period verification enabled
Notes
On changing parameter MODE_ST during operation
command SOFT_RES should be issued.
Modes 0x08, 0x09, 0x0A are not permitted during
calibration via Op.Mode’s ANA_x or DIGx_x.
Table 42: Nonius modes
Output Data Verification
It is possible to verify the counted period when a non-
ius calculation has been completed. Possible settings
include:
1. No verification of counted periods
2. Frequency-dependent verification of counted peri-
ods. Exceeding the maximum master track signal
frequency set by FRQ_TH (see Table 46) disables
the flash counter verification versus nonius cal-
Op. Mode Descriptions Of Nonius Modes
MODE_ST Codes 0x00, 0x01, 0x02
With this mode the processing time is largely deter-
mined by the conversion time of the master track. The
conversion procedure is as follows:
1. A data readout request triggers the conversion of
all selected tracks
2. Following conversion of the master track: syn-
chronization with the internal flash counter and
output of the synchronized position value
3. During data readout: conversion of the remaining
tracks and nonius calculation
4. Generation of NON_CTR with the next data read-
out cycle
MODE_ST Codes 0x03, 0x04
The processing time is largely determined by the sum
of the conversion time of the tracks for conversion. The
conversion procedure is as follows:
1. A data readout triggers the complete conversion
of the set tracks
2. Following conversion of the master track: syn-
chronization with the internal flash counter
3. Following conversion of the remaining tracks: no-
nius calculation and generation of NON_CTR
4. Transmission of the synchronized position value.
The transmitted NON_CTR counts as part of the
current conversion.
MODE_ST Codes 0x05, 0x06, 0x7
The processing time is low as "old" data is transmitted,
the time of sampling is, however, known
Note:
The data from the first readout is invalid following a
SOFT_RES).
The conversion procedure is as follows: