IC-MN_16 Datasheet, PDF (36/62 Pages) IC-Haus GmbH – 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION

iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
I/O INTERFACE
Rev F2, Page 36/62
Protocol
iC-MN can transmit position data according to the SSI
protocol where both data length and error messaging
are configurable. The selected mode of operation for
sine-to-digital conversion can limit the permissible SSI
clock frequency (see Operating Conditions on page
15). The highest possible SSI clock frequency of 4 MHz
is permissible for converter modes with an immediate
data output.
TOS
Code
00
01
10
11
Notes
Addr. 0x4C; bit 1:0
Timeout t_out
Internal clock counts
typ. 16 µs
31-32
typ. 8 µs
15-16
typ. 2 µs
3-4
typ. 1 µs
1-2
One
clock
count
is
equal
to
4
fosc
(see
Char.
A01)
Table 50: Timeout
Figure 15: Example of SSI line signals
Output Data Length
For singleturn data lengths (DL_ST) which are less than
13 bits the SSI data word is zero filled. The optional
error bit is always the final bit of the data word.
If enabled by M2S, multiturn data is always transmitted
upfront the singleturn data.
DL_ST
Code
0x00
...
0x05
...
0x11
The output bit count is determined by parameters
DL_ST, M2S and ESSI:
max(13, DL_ST+ESSI) + MT bits
Example: DL_ST = 0 (≡8 Bit); ESSI = 1.
0x12
...
0x19
0x1A
Notes
Result: 8 bits of data + 4 zeros + 1 error bit are trans-
mitted = 13 bits of data.
Addr. 0x3E; bit 4:0
Bit count
8 bit plus zeroes (+1 error bit)*
...
13 bit (+1 error bit)*
...
25 bit (+1 error bit)*
Bit counts listed below are valid only for multiturn
synchronization mode (s.P. 30 ff.)
26 bit (+1 error bit)*
...
33 bit (+1 error bit)*
39 bit (+1 error bit)*
*) When enabled by ESSI = 1
Table 51: ST Data length
M2S
Code
00
01
10
11
Addr. 0x3F; bit 2:1
Function
no output
MT data output of lowest 4 bits
MT data output of lowest 8 bits
Complete output, MT bit count following DL_MT
Table 52: MT Data output