H27UAG8T2B Datasheet, PDF (9/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

1.5. Array Organization
■ Figure 4. Array organization
8,640 bytes
8,192
448
8,192
448
1 Block
Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
8,640 bytes
8,192
448
8,192
448
1 Block
I/O 7
I/O 0
1 Page = (8,192 + 488 bytes)
1 block = (8,192 + 488) bytes x 256 pages
= (2M + 112K) bytes
1 Device = (8,192 + 488) bytes x 256 pages x 1024 block
= 17,694,720 kbits
Plane 0
Plane 1
1.6. Addressing
Bus cycle
1^st Cycle
2^nd Cycle
3^rd Cycle
4^th Cycle
5^th Cycle
I/O0
A0
A8
A14
A22
A30
I/O1
A1
A9
A15
A23
A31
I/O2
A2
A10
A16
A24
L⁽¹⁾
I/O3
A3
A11
A17
A25
L⁽¹⁾
I/O4
A4
A12
A18
A26
L⁽¹⁾
I/O5
A5
A13
A19
A27
L⁽¹⁾
I/O6
A6
L⁽¹⁾
A20
A28
L⁽¹⁾
Notes:
1. L must be set to Low.
2. The device ignores any additional address input cycle than required.
3. The Address consists of column address (A0~A13), page address (A14 ~ A21), plane address (A22), and
block address (A23 ~ the last address).
I/O7
A7
L⁽¹⁾
A21
A29
L⁽¹⁾
Rev 1.0 / Aug. 2010
9