H27UAG8T2B Datasheet, PDF (30/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
3.14. Multi Plane Cache Read Operation Timings
■ Figure 19. Multi plane cache read operation Timings
Notes:
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The column address will be reset to 0 by the 31h/3Fh command input.
Cache read operation is available only within a block.
Make sure to terminate the operation with 3Fh command. If the page read operation is completed,
issue FFh reset before next operation.
Multi Plane Page addresses are required to be the same.
Multi Plane cache read must be used after Multi plane programmed page, multi plane cache program,
and multi plane copy-back program
Rev 1.0 / Aug. 2010
30