H27UAG8T2B Datasheet, PDF (33/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
3.19. Multi Plane Page Program Operation Timings
■ Figure 25. Multi plane page program operation timing
CE#
CLE
ALE
tWC
WE#
I/Ox
R/B#
A
CE#
80h
Col. Col. Row Row Row DIN
Add1 Add2 Add1 Add2 Add3 N
DIN
N+1
A0 ~ A13 : Valid
A14 ~ A21 Valid (Page M)
A22 : Fixed LOW
A23 ~ A31 : Valid (Block J)
CLE
ALE
tWC
WE#
tADL
RE#
I/Ox
R/B#
81h
Col. Col. Row Row Row DIN
Add1 Add2 Add1 Add2 Add3 N
DIN
N+1
A0 ~ A13 : Valid
A14 ~ A21 Valid (Page M)
A22 : Fixed High
A23 ~ A31 : Valid (Block K)
A
tWB
DIN
M
11h
tDBSY
tWB
DIN
M
10h
tPROG
tWHR
70h
Status
IO 0 = 0, pass
IO 0 = 1, fail
Notes:
1. Any command between 11h and 81h is prohibited except 70h, 78h and FFh
2. t_ADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
3. Multi Plane Page addresses are required to be the same.
Rev 1.0 / Aug. 2010
33