H27UAG8T2B Datasheet, PDF (35/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
3.22. Multi Plane Cache Program Operation Timings
■ Figure 28. Multi plane cache program operation timings
CE#
CLE
ALE
tWC
WE#
I/Ox
R/B#
A
CE#
tADL
80h
Col. Col. Row Row Row
Add1 Add2 Add1 Add2 Add3
DIN
N
A0 ~ A13 : Valid
A14 ~ A21 Valid (Page M)
A22 : Fixed LOW
A23 ~ A31 : Valid (Block J)
CLE
ALE
tWC
WE#
I/Ox
R/B#
tADL
80h
Col. Col. Row Row Row
Add1 Add2 Add1 Add2 Add3
DIN
N
A0 ~ A13 : Valid
A14 ~ A21 Valid (Page M+n)
A22 : Fixed LOW
A23 ~ A31 : Valid (Block J)
tWC
tWB
DIN
M
11h
tDBSY
tADL
81h
Col. Col. Row Row Row
Add1 Add2 Add1 Add2 Add3
DIN
N
A0 ~ A13 : Valid
A14 ~ A21 Valid (Page M)
A22 : Fixed High
A23 ~ A31 : Valid (Block K)
tWC
tWB
DIN
M
11h
tDBSY
tADL
81h
Col. Col. Row Row Row
Add1 Add2 Add1 Add2 Add3
DIN
N
A0 ~ A13 : Valid
A14 ~ A21 Valid (Page M+n)
A22 : Fixed High
A23 ~ A31 : Valid (Block K)
A
DIN
M
15h
tCBSYW
DIN
M
10h
tPROG
Notes:
1. t_PROG = Program time for the last page + Program time for the (last -1)th page - (command input cycle
time + address input cycle time + Last page data loading time)
2. Make sure to terminate the operation with 80h-10h- command sequence. If the operation is terminated, Issue
FFh reset before next operation.
3. Selected Page address except A22 within two blocks must be same.
Rev 1.0 / Aug. 2010
35