H27UAG8T2B Datasheet, PDF (41/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
Notes:
1.
2.
3.
4.
5.
Plane 0 and plane 1 should be selected within the same chip
Only one block should be selected from the each Plane.
Multi Plane cache read is available only within a block per plane.
Selected Page address except for A22 within two blocks must be same.
The operation has to be terminated with "3Fh" command.
4.5. Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Six read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd,
4th, 5th, 6th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued
to it. Figure 37 shows the operation sequence, while 2.10 READ ID data tables explain the byte meaning.
■ Figure 37. Read ID
CLE
WE#
ALE
RE#
I/Ox
t_WHR
90h
00h
ADh
D7h
94h
9Ah
74h
42h
4.6. Read Status Register
The device contains a Status Register which may be read to find out whether read, program or erase operation is com-
pleted, and whether the program or erase operation is completed successfully. After writing Read Status (70h) or Multi
Plane Read Status (78h) command to the command register, a read cycle outputs the content of the Status Register to
the I/O pins only if CE# and RE# are low, whichever occurs last. This two line control allows the system to poll the
progress of each device in multiple memory connections even when R/B# pins are common-wired. Refer to 2.8. STA-
TUS REGISTER CODINGS for specific Status Register definitions and Figure 38, Figure 39 for Read Status. The com-
mand register remains in Read Status mode until further commands are issued to it. Therefore, if the status register is
read during a random read cycle, the read command (00h) should be given before starting read cycles.
■ Figure 38. Read status
CLE
WE#
RE#
I/Ox
70h
Status
Rev 1.0 / Aug. 2010
41