H27UAG8T2B Datasheet, PDF (53/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

■ Figure 52. Interleaved multi plane page read
Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
I/Ox
Address
Address
60h _(3cycle) 60h _(5cycle) 30h
Chip 1
Chip 1
R/B#
(chip 1 internal)
R/B#
(chip 2 internal)
R/B#
(external)
Address
Address
60h _(3cycle) 60h _(3cycle) 30h
Chip 2
Chip 2
78h
Row
Add.1
Row Row
Add.2 Add.3 ^Status
Chip 1
A
Address
00h _(5cycle)
05h
Address
(2cycle)
E0h
Chip 1, plane 0 Chip 1, plane 0
Data output
Chip 1, plane 0
A
I/Ox
R/B#
(chip 1 internal)
R/B#
(chip 2 internal)
R/B#
(external)
Address
00h _(5cycle)
Address
05h _(2cycle)
Chip 1. plane 0
E0h
Data output
Chip 1. plane 0
78h
Row Row Row
Add.1 Add.2 Add.3
Status
Chip 2
00h
Address
(5cycle)
05h
Address
(2cycle)
E0h
Chip 2. plane 0
Data output
00h
Chip 2. plane 0
Address
(5cycle)
05h
Address
(2cycle)
E0h
Chip 2. plane 1
Data output
Chip 2. plane 1
Note:
70h command is prohibited during interleaved operations.
5.3. Interleaved Page Program
Figure 53 show how to perform interleaved PROGRAM PAGE operations. RANDOM DATA INPUT (85h) is permitted
during interleaved PROGRAM PAGE operations.
■ Figure 53. Interleaved page program
I/Ox
80h
R/B#
(chip 1 internal)
Address
(5cycle)
Chip 1
Data Input 10h
R/B#
(chip 2 internal)
R/B#
(external)
80h
Address
(5cycle)
Data Input 10h
Chip 2
78h
Row Row Row
Add.1 Add.2 Add.3
Status
Chip 1
80h
Address
(5cycle)
Data Input 10h
Chip 1
Note:
70h command is prohibited during interleaved operations.
5.4. Interleaved Multi Plane Page Program
Figure 54 shows how to perform interleaved Multi Plane Page Program operations. The interleaved TWO-PLANE PRO-
GRAM PAGE operation must meet two-plane addressing requirements. Random data input (85h) is permitted during
interleaved Multi plane page program operation.
Rev 1.0 / Aug. 2010
53