H27UAG8T2B Datasheet, PDF (40/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
■ Figure 35. Multi plane page read
Page address : Page M
Page address : Page M
Plane address : Fixed “Low”
Plane address : Fixed “High”
Block address : Block J
Block address : Block K
A
I/Ox
60h
Address
(3 Cycle)
60h
Address
(3 Cycle)
30h
R/B#
t_R
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘Low’
A
Block address : Block J
Column address : Valid
B
I/Ox
00h
Address
(5 Cycle)
05h
Address
(2 Cycle)
E0h
Data output
R/B#
B
I/Ox
00h
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘High’
Block address : Block K
Address
(5 Cycle)
05h
Column address : Valid
Address
(2 Cycle)
E0h
Data output
R/B#
4.4. Multi Plane Cache Read (available only within a block)
The device supports multi plane cache read, which enables high read throughput by reading two pages in
parallel. Figure 36 shows the command sequence for the multi plane cache read operation. Both confirm commands,
30h and 33h, are valid for the first page read sequence.
■ Figure 36. Multi plane cache read
A
I/Ox
60h
Address
(3 Cycle)
60h
Address
(3 Cycle)
33h
R/B#
tR
A
I/Ox
31h
Column address : Fixed LOW
Page address : Page M
Plane address : Fixed LOW
B
Block address : Block J
Column address : Valid
00h
Address
(5 Cycle)
05h
Address
(2 Cycle)
E0h
Data output
R/B#
tCBSYR
B
I/Ox
R/B#
Column address : Fixed LOW
Page address : Page M
Plane address : Fixed HIGH
Block address : Block K
Column address : Valid
00h
Address
(5 Cycle)
05h
Address
(2 Cycle)
Eoh
Data output
Rev 1.0 / Aug. 2010
40