H27UAG8T2B Datasheet, PDF (55/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

5.6. Interleaved Multi Plane Block Erase
Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
Figure 56 shows how to perform two types of interleaved Multi Plane Block Erase operations. This operation must meet
two-plane addressing requirements.
■ Figure 56. Interleaved multi plane block erase
I/Ox
60h
Address
(3cycle)
60h
Address
(3cycle)
D0h
Chip 1
Chip 1
R/B#
(chip 1 internal)
R/B#
(chip 2 internal)
R/B#
(external)
60h
Address
(3cycle)
60h
Address
(3cycle)
D0h
Chip 2
Chip 2
78h
Row.
Add 1.
Row. Row.
Add 2. Add. 3
Chip 1
Status
60h
Address
(3cycle)
60h
Address
(3cycle)
D0h
Chip 1
Chip 1
Note:
70h command is prohibited during interleaved operations.
Rev 1.0 / Aug. 2010
55