H27UAG8T2B Datasheet, PDF (56/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
6. OTHER FEATURES
6.1. Data Protection & Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever V_CC is below about 2.0V (3.3V device). WP# pin provides hardware
protection and is recommended to be kept at VIL during power-up and power-down.
The reset command (FFh) must be issued to all dies as the first command after device is power up. Each R/B# will be
busy for maximum of 2ms after reset command is issued. In this time, the acceptable command is 70h or 78h.
■ Figure 57. Data protection and power on / off
VCC
0V
3V device = 2.7V
CE#
WP#
CLE
WE#
ALE
RE#
I/Ox
R/B#
10 ༕
(max)
50 ༕
(min)
Vcc ramp
starts
1ms (max)
tCS
FFh
2 ms
(max)
: Don’t care
2.7V
: Undefined
6.2. Ready / Busy
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back and random read completion. The R/B# pin is normally high and goes to low when the device is busy (after
a reset, read, program, and erase operation). It returns to high when the internal controller has finished the operation.
The pin is an open-drain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor
value is related to tR (R/B#) and current drain during busy (Ibusy), an appropriate value can be obtained with the fol-
lowing reference chart (Figure 58). Its value can be determined by the following guidance.
Rev 1.0 / Aug. 2010
56