H27UAG8T2B Datasheet, PDF (45/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

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H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
tus bit (I/O 6). In addition, the status bit (I/O 5) can be used to determine when the cell programming of the current
data register contents is complete. Pass/fail status of only the previous page (I/O 1) is available upon the return to
Ready state.
The last page of the target programming sequence must be programmed with actual “Page Program” command (10h).
If single plane cache program begins, single plane sequence should be used until single plane cache program is ended.
Pass/fail status is available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status
bit changing to "1", and later I/O 0 with the status of current page upon true Ready (returning from internal program-
ming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked. Refer to 2.8. Status
Register Coding and Figure 43 for more details.
■ Figure 43. Cache program
I/Ox
80h
Address (5 cycle)
R/B#
A
I/Ox
80h
Address (5 cycle)
R/B#
B
I/Ox
80h
Address (5 cycle)
R/B#
Data Input
15h
Data Input
15h
Data Input
10h
A
t_CBSYW
B
t_CBSYW
t_PROG
70h
Status
Pass / Fail status for each page programmed by the Cache Program operation can be detected by the Read Status operation.
I/O 0 : Pass / Fail of the current page program operation.
I/O 1 : Pass / Fail of the previous page program operation.
The Pass / Fail status on I/O 0 and I/O 1 are valid under the following conditions.
Status on I/O 0 : Ready / Busy is Ready state.
The Ready/ Busy is output on I/O 5 by Read Status operation or R/B pin after the 10h command.
Status on I/O 1 : Data Cache Ready / Busy is Ready State.
The Data Cache Ready / Busy is output on I/O 6 by Read Status operation or R/B pin after the 15h command.
I/O 1 =>
I/O 0 =>
Invalid
Invalid
Page1
Invalid
Page1
Page2
80h-add-data-15h
70h
Page 1
R/B# Pin
t_CBSYW
SR
OUT
80h-add-data-15h
70h
SR
OUT
Page 2
t_CBSYW
70h
SR
OUT
Data Cache Ready /Bysy
(I/O6)
Data Cache Ready /Bysy
(I/O5)
Page 1
Page 2
Page N-2
Invalid
80h-add-data-15h
70h
SR
OUT
Page N-1
t_CBSYW
80h-add-data-15h
Page N
Invalid
Invalid
70h
SR
OUT
t_PROG
Page N-1
Page N
70h ^SR
OUT
Page N-1
Page N
During both I/O6 and I/O5 return to high, the Pass/Fail for previous page and current page
can be shown through I/O1 and I/O0 concurrently.
Rev 1.0 / Aug. 2010
45