H27UAG8T2B Datasheet, PDF (54/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
■ Figure 54. Interleaved multi plane page program
I/Ox
80h
Address.
(5cycle)
Data Input
11h
Chip 1
R/B#
(chip 1 internal)
R/B#
(chip 2 internal)
R/B#
(external)
A
I/Ox
R/B#
(chip 1 internal)
78h
Row.
Add.1
Row.
Add.2
Row.
Add.3
Status
Chip 1
R/B#
(chip 2 internal)
R/B#
(external)
81h
Address.
(5cycle)
Data Input
10h
Chip 1
80h
Address.
(5cycle)
Data Input
11h
Chip 1
80h
Address.
(5cycle)
Data Input
11h
Chip 2
A
81h
Address.
(5cycle)
Data Input
10h
Chip 2
81h
Address.
(5cycle)
Data Input
10h
Chip 1
Note:
70h command is prohibited during interleaved operations.
5.5. Interleaved Block Erase
Figure 55 shows how to perform interleaved Block Erase operation.
■ Figure 55. Interleaved block erase
I/Ox
60h
Address
(3cycle)
D0h
Chip 1
R/B#
(chip 1 internal)
R/B#
(chip 2 internal)
R/B#
(external)
60h
Address
(3cycle)
D0h
Chip 2
60h
Address
(3cycle)
D0h
Chip 1
60h
Address
(3cycle)
D0h
Chip 2
Note:
70h command is prohibited during interleaved operations.
Rev 1.0 / Aug. 2010
54