H27UAG8T2B Datasheet, PDF (38/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

4. DEVICE OPERATION
4.1. Page Read
Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
This operation is initialized by 00h-30h to the command register along with followed by five address input cycles. The
8,640 bytes of data within the selected page are transferred to the data registers in less than 200㎲(t_R). The system
controller may detect the completion of this data transfer 200㎲(t_R) by analyzing the output of R/B# pin. Once the
data in a page is loaded into the data registers, they may be read out in 25㎱ cycle time by sequentially pulsing RE#.
The repetitive high to low transitions of the RE# clock make the device output the data starting from the selected col-
umn address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data out-
put command. The column address of next data, which is going to be out, may be changed to the address, which fol-
lows random data output command. Random data output can be operated multiple times, regardless of how many
times it is done in a page.
■ Figure 32. Page read
CLE
CE#
ALE
WE#
R/B#
tR
RE#
I/Ox
00h
Address (5 cycle)
30h
Data Output (Serial Access)
Random data output
Random data output operation changes the column address from which data is being read in the page register. Ran-
dom data output only is issued in Ready state. Refer to Figure 33.
■ Figure 33. Random data output
R/B#
t_R
RE#
I/Ox
00h
Address
(5 cycle)
30h
Data Output
05h
Address
(2 cycle)
E0h
Data Output
Rev 1.0 / Aug. 2010
38