H27UAG8T2B Datasheet, PDF (49/61 Pages) Hynix Semiconductor – 16Gb (2048M x 8bit) NAND Flash

■ Figure 47. Multi plane Copyback program
Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
Page address : Page M
Page address : Page M
Plane address : Fixed “Low”
Plane address : Fixed “High”
Block address : Block J
Block address : Block K
A
I/Ox
60h
Address
(3 Cycle)
60h
Address
(3 Cycle)
35h
R/B#
t_R
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “Low”
A
Block address : Block J
Column address 1,2 : Valid
B
I/Ox
00h
Address
(5 Cycle)
05h
Address
(2 Cycle)
E0h
Data output
R/B#
Column address : Valid
Page address : Page N
Plane address : Fixed “Low”
B
Block address : Block P
Column address 1,2 : Valid
C
I/Ox
85h
Address
(5 Cycle)
Data 85h
Address
(2 Cycle)
Data
11h
R/B#
t_DBSY
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “High”
C
Block address : Block K
Column address 1,2 : Valid
D
I/Ox
00h
Address
(5 Cycle)
05h
Address
(2 Cycle)
E0h
Data output
R/B#
Column address : Valid
Page address : Page N
Plane address : Fixed “High”
D
Block address : Block Q
Column address 1,2 : Valid
I/Ox
81h
Address
(5 Cycle)
Data
85h
Address
(2 Cycle)
Data
10h
R/B#
t_PROG
4.13. Block Erase
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command (60h). Only address A22 to A31 is valid while A14 to A21 is ignored. The Erase Confirm command
(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup fol-
lowed by execution command ensures that memory contents are not accidentally erased due to external noise condi-
tions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and
erase verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register. The sys-
Rev 1.0 / Aug. 2010
49