HY5PS1G821M Datasheet, PDF (76/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and
its complement, DQS. This distinction in timing methods is guaranteed by design and characterization.
Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must
be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation.
DQS/
DQS
DQ
DM
DQS
DQS
t_WPRE
t_DQSH
t_DQSL
D
t_DS
DMin
D
t_DS
DMin
D
t_DH
DMin
t_WPST
D
t_DH
DMin
Figure -- Data input (write) timing
CK
CK/CK
CK
DQS/DQS
DQ
t_CH
t_CL
DQS
DQS
t_RPRE
t_DQSQmax
Q
t_QH
Q
Q
t_DQSQmax
Figure -- Data output (read) timing
t_RPST
Q
t_QH
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
Rev. 0.2 / Oct. 2005
76