HY5PS1G821M Datasheet, PDF (47/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
2.8 Refresh Commands
DDR2 SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of
two ways: by an explicit Auto-Refresh command, or by an internally timed event in SELF REFRESH mode.
Dividing the number of device rows into the rolling 64ms interval, tREFI, which is a guideline to controllers for
distributed refresh timing. For example, a 512Mb DDR2 SDRAM has 8192 rows resulting in a tREFI of 7.8㎲.
To avoid excessive interruptions to the memory controller, higher density DDR2 SDRAMS maintain 7.8㎲
average refresh time and perform multiple internal refresh bursts. In these cases, the refresh recovery times,
tRFC an tXSNR are extended to accomodate these internal operations.
2.8.1 Auto Refresh Command
AUTO REFRESH is used during normal operation of the DDR2 SDRAM. This command is nonpersistent, so
it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command.
When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the
Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Pre-
charge time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the
device, supplies the bank address during the refresh cycle. No control of the external address bus is required
once this cycle has started.
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A
delay between the Refresh command (REF) and the next Activate command or subsequent Refresh com-
mand must be greater than or equal to the Refresh cycle time (tRFC).
To allow for improved efficiency in scheduling andswitching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight Refresh commands can be posted to any given DDR2
SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh
command is 9 * tREFI.
T0
T1
T2
CK/CK
CKE
High
> = t_RP
CMD ^Precharge
NOP
NOP
T3
> = t_RFC
REF
Tm
REF
Tn
Tn + 1
> = t_RFC
NOP
ANY
2.8.2 Self Refresh Operation
The Self Refresh command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is
powered down. When in the Self Refresh mod, the DDR2 SDRAM retains data without external clocking.
The DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh
Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.
ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS
command. Once the Command is registered, CKE must be held low to keep the device in Self Refresh mode.
The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon existing Self
Refresh. When the DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are
“don’t care”. The DRAM initiates a minimum of one Auto Refresh command internally within tCKE period once
it enters Self Refresh mode.The clock is internally disabled during Self Refresh Operation to save power. The
minimum time that the DDR2 SDRAM must remain in Self Refresh mode is tCKE. The user may change the
external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however,
the clock must be restarted and stable before the device can exit Self Refresh operation.
Rev. 0.2 / Oct. 2005
47