HY5PS1G821M Datasheet, PDF (42/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Burst Write followed by Precharge
Minium Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge
Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion
of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay.
Example 1: Burst Write followed by Precharge: WL = (RL-1) =3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Posted CAS
WRITE A
NOP
NOP
DQS/DQS
DQs
WL = 3
NOP
NOP
NOP
NOP
NOP
Completion of the Burst Write
> = WR
Precharge A
DIN A₀ DIN A₁ DIN A₂ DIN A₃
Example 2: Burst Write followed by Precharge: WL = (RL-1) = 4
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK/CK
CMD ^{Posted CAS}
WRITE A
NOP
NOP
DQS/DQS
DQs
WL = 4
NOP
NOP
NOP
NOP
NOP
Completion of the Burst Write
> = t_WR
Precharge A
DIN A₀ DIN A₁ DIN A₂ DIN A₃
Rev. 0.2 / Oct. 2005
42