HY5PS1G821M Datasheet, PDF (72/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
7. AC Timing Specifications
7.1 Timing Parameters by Speed Grade
Parameter
DQ output access time from
CK/CK
DQS output access time from
CK/CK
CK high-level width
CK low-level width
CK half period
Symbol
tAC
tDQSCK
tCH
tCL
tHP
Clock cycle time, CL=x
tCK
DQ and DM input hold time
tDH
DQ and DM input setup time
tDS
Control & Address input pulse
width for each input
tIPW
DQ and DM input pulse width for
each input
tDIPW
Data-out high-impedance time
tHZ
from CK/CK
DQS low-impedance time from
CK/CK
tLZ
(DQS)
DQ low-impedance time from
CK/CK
tLZ
(DQ)
DQS-DQ skew for DQS and
associated DQ signals
tDQSQ
DQ hold skew factor
tQHS
DQ/DQS output hold time from
tQH
DQS
Write command to first DQS
latching transition
tDQSS
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS falling edge to CK setup time tDSS
DQS falling edge hold time from
CK
tDSH
Mode register set command cycle tMRD
time
DDR2-400 3-3-3
min
max
-600
+600
DDR2-533 4-4-4
Unit
min
max
-500
+500
ps
-500
+500
-450
+450
ps
0.45
0.45
min(tCL,
tCH)
5000
400
400
0.6
0.55
0.55
-
8000
-
-
-
0.45
0.45
min(tCL,
tCH)
3750
350
350
0.6
0.55
tCK
0.55
tCK
-
ps
8000
ps
-
ps
-
ps
-
tCK
0.35
-
0.35
-
tCK
-
tAC max
-
tAC max
ps
tAC min
tAC max
tAC min
tAC max
ps
2*tAC min
tAC max
2*tAC min tAC max
ps
-
350
-
300
ps
-
450
-
400
ps
tHP - tQHS
-
tHP - tQHS
-
ps
WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK
0.35
-
0.35
-
tCK
0.35
-
0.35
-
tCK
0.2
-
0.2
-
tCK
0.2
-
0.2
-
tCK
2
-
2
-
tCK
Note
11,12
15
6,7,8
6,7,8
13
12
Rev. 0.2 / Oct. 2005
72