HY5PS1G821M Datasheet, PDF (30/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Burst Read Operation: RL = 3 (AL = 0 and CL = 3, BL = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD ^{READ A}
NOP
NOP
DQS/DQS
DQs
CL =3
RL = 3
NOP
=< t_DQSCK
NOP
NOP
NOP
NOP
DOUT A₀ DOUT A₁ DOUT A₂ DOUT A₃ DOUT A₄ DOUT A₅ DOUT A₆ DOUT A₇
NOP
Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4
T0
T1
Tn-1
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
CK/CK
CMD
Post CAS
READ A
DQS/DQS
DQ’s
NOP
NOP
Post CAS
WRITE A
NOP
t_RTW (Read to Write turn around time)
NOP
NOP
RL =5
WL = RL - 1 = 4
DOUT A₀ DOUT A₁ DOUT A₂ DOUT A₃
NOP
NOP
DIN A₀ DIN A₁ DIN A₂ DIN A₃
The minimum time from the burst read command to the burst write command is defined by a read-to-write-
turn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
Rev. 0.2 / Oct. 2005
30