HY5PS1G821M Datasheet, PDF (73/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Parameter
Symbol
Write postamble
Write preamble
Address and control input hold
time
Address and control input setup
time
Read preamble
Read postamble
Active to precharge command
Active to Read or Write
(with and without Auto-Precharge)
delay
Auto-Refresh to Active/Auto-
Refresh command period
Precharge Command Period
tWPST
tWPRE
tIH
tIS
tRPRE
tRPST
tRAS
tRCD
tRFC
tRP
Active to Active/Auto-Refresh
command period
Active to active command period
for 1KB page size(x4,x8)
Active to active command period
for 2KB page size(x16)
CAS to CAS command delay
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command
delay
Internal read to precharge
command delay
Exit self refresh to a non-read
command
Exit self refresh to a read
command
Exit precharge power down to any
non-read command
tRC
tRRD
tRRD
tCCD
tWR
tDAL
tWTR
tRTP
tXSNR
tXSRD
tXP
DDR2-400 3-3-3
min
max
0.4
0.6
0.25
-
600
-
600
-
0.9
1.1
0.4
0.6
40*
70000
15
-
105
-
15
-
55*
-
7.5
-
10
-
2
15
-
WR+tRP
-
2
-
7.5
tRFC + 10
200
-
2
-
DDR2-533 4-4-4
min
max
0.4
0.6
0.25
-
500
-
500
-
0.9
1.1
0.4
0.6
45
70000
15
-
Unit Note
tCK
10
tCK
ps
5,7,9
ps
5,7,9
tCK
tCK
ns
3
ns
105
-
ns
15
-
ns
60
-
ns
7.5
-
ns
4
10
-
ns
4
2
15
WR+tRP
tCK
-
ns
-
tCK
14
2
-
tCK
7.5
ns
3
tRFC + 10
ns
200
-
tCK
2
-
tCK
Rev. 0.2 / Oct. 2005
73