HY5PS1G821M Datasheet, PDF (20/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
1
0
1
0
Other Combinations
Decrease by 1 step
Decrease by 1 step
Reserved
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the
following timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected
by
MRS addressing mode (ie. sequential or interleave).
OCD adjust mode
CMD EMRS
NOP
CK
CK
WL
DQS_in
DQ_in
DM
NOP
NOP
NOP
DQS
tDS tDH
DT0 _DT1 DT2 DT3
OCD calibration mode exit
NOP
EMRS
NOP
WR
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver
impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output
drivers are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.
Enter Drive mode
CMD
EMRS
NOP
NOP
OCD calibration mode exit
NOP
EMRS
CK
CK
Hi-Z
DQS
DQS
DQ
Hi-Z
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0)
DQs high for Drive(1)
DQs low for Drive(0)
tOIT
Rev. 0.2 / Oct. 2005
tOIT
20