HY5PS1G821M Datasheet, PDF (14/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
2.3.2.1 DDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls
CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to
make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined,
therefore the mode register must be written after power-up for proper operation. The mode register is written
by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A15.
The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode reg-
ister. The mode register set command cycle time (tMRD) is required to complete the write operation to the
mode register. The mode register contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. The mode register is
divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and
8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type
is defined by A3, CAS latency is defined by A4 ~ A6. The DDR2 doesn’t support half clock latency mode. A7
is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recov-
ery time tWR is defined by A9 ~ A11. Refer to the table for specific codes.
BA2 BA1 BA0 A15 ~ A13 A12 _{A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0} Address Field
0*¹ 0 0
0*¹ PD
WR
DLL TM CAS Latency BT Burst Length ^{Mode Register}
A8 DLL Reset
0
No
1
Yes
A7
mode
0 Normal
1
Test
A3 Burst Type Burst Length
0 Sequential
A2 A1 A0 BL
1 Interleave
010 4
011 8
A12
Active power
down exit time
0 Fast exit(use tXARD)
Write recovery for autoprecharge
A11 A10 A9 WR(cycles)
0 0 0 Reserved ^*2
1 Slow exit(use tXARDS)
0
01
2
0
BA1 BA0
MRS mode
0
00
MRS
1
01
EMRS(1)
1
1 0 EMRS(2): Reserved ₁
1 1 EMRS(3): Reserved ₁
10
11
00
01
10
11
3
4
5
6
Reserved
Reserved
CAS Latency
A6 A5 A4 Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2(optional)
0 11
3
1 00
4
1 01
5
1 10
6
1 1 1 Reserved
*1 : BA2 and A13~A15 are reserved for future use and must be programmed to 0 when setting the mode register.
* 2: WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min.
WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer
(WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with
tRP to determine tDAL.
Rev. 0.2 / Oct. 2005
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