HY5PS1G821M Datasheet, PDF (34/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
Tn
CK/CK
CMD ^{WRITE A}
NOP
DQS/
DQS
DQs
WL = RL - 1 = 2
NOP
< = t_DQSS
NOP
NOP
NOP
Completion of
the Burst Write
Precharge
NOP
Bank A
Activate
DIN A₀ DIN A₁ DIN A₂ DIN A₃
> = WR
> = tRP
Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4
T0
T1
T2
T3
T4
T5
CK/CK
Write to Read = CL - 1 + BL/2 + tWTR
CMD ^NOP
NOP
DQS/
DQS
DQS
DQS
WL = RL - 1 = 4
DQ
NOP
NOP
Post CAS
READ A
NOP
DIN A₀ DIN A₁ DIN A₂ DIN A₃
AL = 2
> = tWTR
T6
T7
T8
T9
NOP
NOP
NOP
RL =5
CL = 3
DOUT A₀
The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 +
tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from
the input buffer into sense amplifiers in the array. tWTR is defined in AC spec table of this data sheet.
Rev. 0.2 / Oct. 2005
34