HY5PS1G821M Datasheet, PDF (50/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Read to power down entry
T0
CK
CK
CMD
CKE
DQ
DQS
DQS
T0
T1
T2
RD
BL=4
T1
T2
Tx
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
Read operation starts with a read command and
CKE should be kept high until the end of burst operation.
AL + CL
QQQQ
Tx
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CMD
CKE
DQ
DQS
DQS
RD
BL=8
CKE should be kept high until the end of burst operation.
AL + CL
QQQQQQQQ
Read with Autoprecharge to power down entry
T0
CK
CK
CMD
CKE
DQ
DQS
DQS
T0
T1
T2
Tx
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
RDA
BL=4
PRE
AL + BL/2
with tRTP = 7.5ns
& tRAS min satisfied
AL + CL
QQQQ
CKE should be kept high
until the end of burst operation.
T1
T2
Tx
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CMD
CKE
RDA
BL=8
DQ
DQS
DQS
Rev. 0.2 / Oct. 2005
AL + BL/2
with tRTP = 7.5ns
& tRAS min satisfied
PRE
Start internal precharge
AL + CL
QQQQQQQQ
CKE should be kept high
until the end of burst operation.
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