HY5PS1G821M Datasheet, PDF (15/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
2.3.2.2 DDR2 SDRAM Extended Mode Register Set
EMRS(1)
The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency,
ODT, DQS disable, OCD program, RDQS enable. The default value of the extended mode register(1) is not defined,
therefore the extended mode register(1) must be written after power-up for proper operation. The extended mode regis-
ter(1) is written by asserting low on CS, RAS, CAS, WE, high on BA0 and low on BA1, while controlling the states of
address pins A0 ~ A15. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the
extended mode register(1). The mode register set command cycle time (tMRD) must be satisfied to complete the write
operation to the extended mode register(1). Mode register contents can be changed using the same command and clock
cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or
disable. A1 is used for enabling a half strength output driver. A3~A5 determines the additive latency, A7~A9 are used for
OCD control, A10 is used for DQS disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and
upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time
the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be
issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for syn-
chronization to occur may result in a violation of the tAC or tDQSCK parameters.
Rev. 0.2 / Oct. 2005
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