HY5PS1G821M Datasheet, PDF (60/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

5.2 DC & AC Logic Input Levels
5.2.1 Input DC Logic Level
Symbol
V_IH(dc)
V_IL(dc)
Parameter
dc input logic high
dc input logic low
Min.
VREF + 0.125
- 0.3
Max.
VDDQ + 0.3
VREF - 0.125
1HY5PS12421(L)M
HY5PS12821(L)M
Units
V
V
Notes
5.2.2 Input AC Logic Level
Symbol
V_IH (ac)
V_IL (ac)
Parameter
ac input logic high
ac input logic low
Min.
VREF + 0.250
-
Max.
-
VREF - 0.250
Units
V
V
Notes
5.2.3 AC Input Test Conditions
Symbol
V_REF
V_SWING(MAX)
SLEW
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5 * V_DDQ
1.0
1.0
Units
V
V
V/ns
Notes
1
1
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V_REF level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from V_IL(dc) to V_IH(ac) min for rising edges and the range
from V_IH(dc) to V_IL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
V_SWING(MAX)
delta TF
Falling Slew = ^{VREF - VIL(ac) max}
delta TF
delta TR
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
Rising Slew = ^{VIH(ac)min - VREF}
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 0.2 / Oct. 2005
60