HY5PS1G821M Datasheet, PDF (37/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
2.5.5 Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent
with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and
though used in a uni-directional manner, is internally loaded identically to data bits to insure matched sys-
tem timing. DM of x4 and x16 bit organization is not used during read cycles. However DM of x8 bit organi-
zation can be used as RDQS during read cycles by EMRS(1) settng.
Data Mask Timing
DQS/
DQS
DQ
DM
tDS tDH
tDS tDH
Data Mask Function, WL=3, AL=0, BL = 4 shown
Case 1 : min tDQSS
CK
CK
COMMAND
Write
tDQSS
tWR
DQS/DQS
DQ
DM
Case 2 : max tDQSS
DQS/DQS
DQ
DM
tDQSS
Rev. 0.2 / Oct. 2005
37