HY5PS1G821M Datasheet, PDF (48/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
The procedure for existing Self Refresh requires a sequence of commands. First, the clock must be stable
prior to CKE going back HIGH. Once Self Refresh Exit command is registered, a delay equal or longer than
the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must
remain high for the entire Self Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh,
the DDR2 SDRAM can be put back into Self Refresh mode after tXSRD expires.NOP or deselect commands
must be registered on each positive clock edge during the Self Refresh exit interval. ODT should also be
turned off during tXSRD.
The Use of Self Refresh mode introduce the possibility that an internally timed refresh event can be missed
when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires
a minimum of one extra auto refresh command before it is put back into Self Refresh mode.
T0
T1
T2
tCK
tCH tCL
CK
CK
CKE
ODT
tIS
CMD
T3
T4
T5
T6
tRP*
tIS
tAOFD
tIS tIH
Self
Refresh
Tm
Tn
> = tXSNR
> = tXSRD
tIS
NOP
NOP
NOP
Valid
- Device must be in the “All banks idle” state prior to entering Self Refresh mode.
- ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again
when tXSRD timing is satisfied.
- tXSRD is applied for a Read or a Read with autoprecharge command
- tXSNR is applied for any command except a Read or a Read with autoprecharge command.
Rev. 0.2 / Oct. 2005
48