HY5PS1G821M Datasheet, PDF (31/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Seamless Burst Read Operation: RL = 5, AL = 2, and CL = 3, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD ^{Post CAS}
READ A
NOP
Post CAS
READ B
NOP
NOP
DQS/DQS
DQs
AL = 2
RL = 5
CL =3
NOP
NOP
NOP
NOP
DOUT A₀ DOUT A₁ DOUT A₂ DOUT A₃ DOUT B₀ DOUT B₁ DOUT B₂
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4
operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different
banks as long as the banks are activated.
Rev. 0.2 / Oct. 2005
31