HY5PS1G821M Datasheet, PDF (36/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Writes interrupted by a write
Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write inter-
rupt is not allowed.
Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)
CK/CK
CMD ^NOP
Write A
NOP
Write B
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS
DQs
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
Notes:
1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read
command or Precharge command is prohibited.
3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write
burst interrupt timings are prohibited.
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with Auto Precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another Write with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced
to actual burst. For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts
with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
Rev. 0.2 / Oct. 2005
36