HY5PS1G821M Datasheet, PDF (33/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
2.5.4 Burst Write Operation
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined
by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven
low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins
at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write
cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is
completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins
will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the com-
pletion of the burst write to bank precharge is the write recovery time (WR).
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the
setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its com-
plement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that
when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied
externally to VSS through a 20 ohm to 10 Kohm resistor to insure proper operation.
DQS/
DQS
DQ
DM
DQS
DQS
t_WPRE
t_DQSH
t_DQSL
D
t_DS
DMin
D
t_DS
DMin
D
t_DH
DMin
t_WPST
D
t_DH
DMin
Data input (write) timing
Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
Tn
CK/CK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
DQS/DQS
DQs
WL = RL - 1 = 4
NOP
< = t_DQSS
NOP
NOP
NOP
Completion of
the Burst Write
Precharge
DIN A₀ DIN A₁ DIN A₂ DIN A₃
> = WR
Rev. 0.2 / Oct. 2005
33