HY5PS1G821M Datasheet, PDF (71/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
For purposes of IDD testing, the following parameters are to be utilized
Parameter
CL(IDD)
tRCD(IDD)
tRC(IDD)
tRRD(IDD)-x4/x8
tRRD(IDD)-x16
tCK(IDD)
tRASmin(IDD)
tRASmax(IDD)
tRP(IDD)
tRFC(IDD)-512Mb
DDR2-667
5-5-5
5
6-6-6
6
15
18
60
63
7.5
9
3
45
70000
15
7.5
9
3
45
70000
18
105
105
DDR2-533
4-4-4
4
15
5-5-5
5
18.75
60
63.75
7.5
7.5
10
10
3.75
3.75
45
45
70000
70000
15
18.75
105
105
DDR2-400
3-3-3
3
15
4-4-4
4
20
55
65
7.5
7.5
10
10
5
5
40
45
70000
70000
15
20
105
105
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum ^tRC(IDD) without violating ^tRRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 4/4/4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
-DDR2-533 5/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
Rev. 0.2 / Oct. 2005
71