HY5PS1G821M Datasheet, PDF (32/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Reads interrupted by a read
Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read inter-
rupt is not allowed.
Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)
CK/CK
CMD ^{Read A}
NOP
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS
DQs
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
Note
1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write
command or Precharge command is prohibited.
3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read
burst interrupt timings are prohibited.
4. Read burst interruption is allowed to any bank inside DRAM.
5. Read burst with Auto Precharge enabled is not allowed to interrupt.
6. Read burst interruption is allowed by another Read with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced
to actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst
length set in the mode register and not the actual burst (which is shorter because of interrupt).
Rev. 0.2 / Oct. 2005
32