HY5PS1G821M Datasheet, PDF (18/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
2.3.2.3 Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every
calibration mode command should be followed by “OCD calibration mode exit” before any other command
being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termian-
tion) should be carefully controlled depending on system environment.
MRS shoud be set before entering OCD impedance adjustment and ODT should
be carefully controlled depending on system environment
Start
EMRS: OCD calibration mode exit
EMRS: Drive(1)
DQ & DQS High; DQS Low
EMRS: Drive(0)
DQ & DQS Low; DQS High
ALL OK
Test
Need Calibration
EMRS: OCD calibration mode exit
ALL OK
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS :
Enter Adjust Mode
EMRS :
Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec, or NOP
BL=4 code input to all DQs
Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
Rev. 0.2 / Oct. 2005
18